1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory characterized in the arrangement of contacts on active areas of the semiconductor memory.
2. Description of the Related Art
In order to implement a large capacity, low cost NAND flash EEPROM, miniaturization based on a scaling law is essential. However, since manufacturing conditions become more strict as miniaturization progresses, the current process technology for implementing miniaturized NAND flash EEPROM cannot keep up.
The structure of NAND flash EEPROM can be largely divided into cell arrays and peripheral circuits. Less strict design rules than those for memory cell transistors apply to the peripheral circuits for satisfying desired transistor performance and specifications such as current and withstand voltage. On the contrary, miniaturization is always being pursued to the limit of process technology because high transistor performance of each memory cell transistor is not in great demand, and a systematic layout is possible.
With a conventional NAND flash EEPROM, (1) active area/device isolation region pitch, (2) gate electrode pitch, (3) pitch of bit line contacts (CB) on active areas, and (4) bit line pitch may be set to a minimum pitch. Leading-edge, costly fabrication apparatuses and materials must be adopted in order to implement the above-discussed processing on a minimum pitch basis. Accordingly, the more minimum pitch locations exist, the more the cost increases, resulting in a loss of product competitiveness.
The process dealing particularly with (3), above, i.e., the pitch between bit line contacts (CB) on active areas is extremely difficult since the aspect ratio of contact holes during processing goes to a maximum. With the conventional NAND flash EEPROM, contacts on active areas are typically formed in a horizontal row along a word line length. Since the contact holes are formed to have forward-tapered shapes, the inter-contact distance at the top of the contact hole becomes extremely short when trying to achieve a half pitch at the bottom of the contact holes. These adjacent contacts may trigger short circuits between bit lines for various reasons. The first reason is described forthwith. Before embedding metallic material and/or conductive material such as polysilicon in the contact holes, it is common to perform wet (or dry) etching for the purpose of removing the natural oxidized film from the semiconductor substrate surface. Since this etching also simultaneously removes the interlayer films, which separate each contact, holes may be formed in the interlayer films due to a change in etching rate. Such operation may cause possible short circuits between bit lines. The second reason is that when a dielectric breakdown due to repeated voltage application generates an electrical leakage current as any remaining interlayer film is too thin.
If it is possible to have less stringent pitch requirements between bit line contacts (CB) on active areas, it is possible to reduce processing difficulty. As a result, for development of next-generation memory cell transistors, intensively investing financial and human resources in development of processes needed for the areas believed to not allow process margins in the (1) active area/device isolation region pitch and the (2) gate electrode pitch becomes possible. In addition, since leading edge technology processes needs not be introduced, costs may be reduced.
An example of a nonvolatile semiconductor memory has been described by referring to NAND flash EEPROM; however, the same consideration applies for a memory with another structure or operation method. For example, NOR, DINOR, AND, and AG-AND type devices, which has assist gates adjacent to the floating gates, are typical as other nonvolatile semiconductor memories (see for reference Y. Sasago, et. al, “10-MB/s Multi-Level Programming of Gb-Scale Flash Memory Enabled by New AG-AND Cell Technology”, Technical Digests of International Electron Devices Meeting, 2002 IEEE, 21.6.1, p. 952-954).
With these structures, in order to connect memory transistors or select gate transistors to bit lines, there are active areas in which contacts are densely aligned. Therefore, the above problems are common to all such devices.
A conventional nonvolatile semiconductor memory, as shown in FIG. 40, includes device isolation regions 59; active areas 60; memory cell block regions 62, which include a plurality of memory cell units formed parallel in the active areas 60, as well as select gate lines SGU and SGL and word lines WL; bit line contacts 64 and source line contacts 65 arranged in the active areas 60; bit lines BL connected to the bit line contacts 64; and a source line 63 extending in a direction orthogonal to the bit lines BL and connected to the source line contacts 65. The bit lines contacts 64 in the active areas are formed in horizontal rows along the word line WL length, where with a conventional NAND flash EEPROM, the pitch thereof is equal to the pitch between the active areas 60. These adjacent contacts may trigger short circuits between bit lines for various reasons.
Technology for formation of contact holes for the bit line contacts 64 aligned in horizontal rows as shown in FIG. 40 demonstrates some improvement as lithography and etching technologies progress, however, the technology is approaching its limit. As the simplest solution, a method of staggering the positions of the bit line contacts is proposed. With this method, staggering the bit line contacts 64 allows sufficient distance therebetween. However, as is apparent from FIG. 41, there is a necessity for sufficient space between the memory cell block regions 62. However, increasing this area is a problem.
Here, given that LSTI denotes the width of each of the device isolation regions 59, LAA denotes the width of each of the active areas 60, and LCB denotes the diameter of each of the bit line contacts 64, distance L1 between the bit line contacts 64 can be represented byL1=LAA+LSTI−LCB  (1)As miniaturization progresses, distance L1 between the bit line contacts 64 becomes shorter, and adjacent bit line contacts 64 can easily short circuit.
Accordingly with a nonvolatile semiconductor memory typified by a NAND EEPROM, there are problems where the distance between bit line contacts CB becomes narrower, and adjacent bit line contacts can easily short circuit.